Scaling of the gate dielectric (or gate insulator) is a challenge in improving performance of advanced field effect transistors (FETs). A gate dielectric with equivalent oxide thickness (EOT) of around 1 nm is desired for some FETs, e.g., in 45 nm technology. In a FET employing a silicon oxide based gate dielectric (e.g., SiO2), the leakage current through the gate dielectric increases exponentially with the decrease in the thickness of the gate dielectric. When the thickness of a silicon oxide based gate dielectric is at or below about 1 to 2 nm, the gate leakage current typically becomes too high, resulting in higher power consumption than is acceptable for a given application. High-dielectric-constant (high-k) gate dielectrics provide a way of scaling down the thickness of gate dielectrics without an excessive increase in gate leakage current. Hafnium based materials are candidates for gate dielectric materials. However, studies have revealed an undesirably high threshold voltage (Vt) in the case of p-channel metal oxide semiconductor field effect transistors (MOSFETs) having hafnium based high-k dielectrics on silicon based channels.